Phase-Locked Loop (“PLL”) circuits are electrical circuits that are commonly used for controlling the frequency of digital and analog electrical signals while maintaining a constant phase. For example, PLL circuits can be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits.
FIG. 1 schematically illustrates a PLL circuit 10 configured as a frequency multiplier. A purpose of the PLL circuit 10 in FIG. 1 is to generate an output frequency signal, CKfb, which is a multiple of and in phase with an input frequency signal CKin. Accordingly, the PLL circuit 10 multiplies the frequency of the input signal CKin, while maintaining a constant phase. The illustrative PLL circuit 10 includes a first frequency divider 14, a phase detector 16, a charge pump 18, a voltage-controlled oscillator 20, and a second frequency divider 22. The voltage-controlled oscillator (VCO) 20 is configured to generate an output signal (shown as signal CKout in FIG. 1), the frequency of which is controlled by an input voltage to the VCO 20. In certain applications, the output signal CKout can be provided to clock distribution circuitry 26, which distributes the CKout signal to a variety of other electronic components, as shown in FIG. 1. The input voltage to the VCO 20 is a signal from the charge pump 18, which is adjusted to cause the PLL to lock. The phase detector 16 compares the respective phases of the input signal CKin and the feedback signal CKfb and generates an output signal based upon the difference between the two phases. Frequency divider 14 and frequency divider 22 are used to modify the frequency of the input signal CKin to a desired frequency for the output and feedback signals CKout and CKfb. In particular, frequency divider 22 is configured to decrease the frequency of the CKfb feedback signal, which, because of the nature of the PLL circuit 10, ultimately tends to multiply the frequency of the output signal CKout and CKfb relative to the input signal CKin. Similarly, frequency divider 14 is configured to reduce the frequency of the output signal CKout and CKfb relative to the input signal CKin. One of ordinary skill in the art will recognize that the specifications of the frequency dividers 14 and 22 can be varied relative to each other to generate a wide variety of different output frequencies CKout and CKfb for a given input frequency CKin.
In operation, the PLL circuit 10 set forth in FIG. 1 functions as follows. The Vcntl voltage signal is applied to the VCO 20, which generates an output signal CKout having a frequency that corresponds to the Vcntl voltage signal. The CKout signal propagates through the clock distribution circuitry 26 producing a phase-delayed feedback version of CKout, referred to as CKfb. When an input signal CKin is provided to the PLL circuit 10, the phase detector 16 detects a difference in the signal phase between the input signal CKin and the feedback signal CKfb. The output of the phase detector 16 and charge pump 18 is a voltage signal that corresponds to the phase difference detected by the phase detector 16. The voltage signal is provided to the VCO 20, which ultimately adjusts the frequency of output signal CKout. The feedback loop of the output signal CKout to CKfb causes the phase of the output signal CKfb to “lock” on the phase of the input signal CKin. As indicated above, the frequency dividers 14 and 22 are configured to adjust the frequency of the output signals CKout and CKfb by a particular factor relative to the input signal CKin. For example, in FIG. 1, if frequency divider 22 is configured to divide the frequency of the feedback signal CKfb by a factor of X, and if the frequency divider 14 is configured to divide the frequency of the input signal CKin by a factor of Y, the output signal CKout will ultimately have a frequency that is X/Y times the frequency of the input signal CKin.
PLL circuits, like the illustrative PLL circuit 10 shown in FIG. 1, can be “started” in a variety of ways. For example, it is known to apply a Vref signal to the PLL control voltage Vcntl for an extended period of time to “start” the PLL circuit generating an oscillating output signal. However, depending on the level of the Vref signal, the PLL circuit may not always start or it may start too fast. For example, if the Vref signal is too low, the frequency of the output signal CKout from the VCO 20 may be too low for the PLL to “lock” on an input frequency. Conversely, if the Vref signal is too high, the frequency of the output signal CKout may be greater than the maximum frequency of the clock distribution circuitry 26, which may damage the clock distribution circuitry 26 and/or provide inaccurate output signals. For instance, if the frequency of the CKout signal exceeds the maximum input frequency of the clock distribution circuitry 26, then the feedback signal CKfb will not contain all the clock edges of CKout. CKfb will appear to be a lower frequency than CKout, rather than just a phase-delayed version of CKout. This could cause the PLL circuit 10 to increase the frequency of the CKout signal, thereby perpetuating the problem.